1. Field of the Invention
The present invention relates to a bus control for a small computer system interface (called "SCSI" hereinafter) which is one interface for peripheral instruments of a small computer, and more specifically to a SCSI bus control in the case that a first in-first out memory (called "FIFO" hereinafter) is used for transmitting information to an SCSI bus and receiving information from the SCSI bus.
2. Description of Related Art
A conventional information transfer in the SCSI can be divided into an asynchronism transfer in which the information is transferred by a perfect handshake between a transfer request signal (called "REQ signal" hereinafter) driven by a target and a transfer acknowledge signal (called "ACK signal" hereinafter) driven by an initiator, and a synchronism transfer in which a REQ signal can be sent without confirming the receipt of the ACK signal. One typical example of the asynchronism transfer is illustrated in FIG. 1, and a typical example of the synchronism transfer is illustrated in FIG. 2. In these figures, the mark "x" in the SCSI data bus indicates data being transferred.
In the conventional SCSI bus control system, when an initiator receives information, the initiator will inactivate the ACK signal for a last information transmission, without checking an empty of the FIFO used for receiving information from an SCSI bus (and also used for transmitting information to the SCSI bus). Thereafter, when a reading of information from the FIFO is completed and the FIFO becomes empty, a transfer system is then initialized. On the other hand, when the initiator has inactivated the ACK signal for the last information transmission, the target which transmits information to the initiator confirms the completion of the transfer phase, and then, can go into a next phase.
Therefore, if the transfer of information from a target to an initiator provided with FIFO is controlled in the conventional SCSI bus control system, there is possibility that the target changes its phase when information still remains in the FIFO. In this situation, if a phase transferring information from the target to the initiator in a synchronism transfer mode is started, the initiator is forced to receive the transmitted information, though the information sent in the preceding phase still remains in the FIFO. As a result, when the information sent in the preceding phase has been read or cleared from the FIFO, the information sent in the next phase already exists in the FIFO, and therefore, the transfer system can no longer initiate the transfer system.